This application claims the benefit of Korean Patent Application No. 2002-0021054, filed on Apr. 17, 2002, which is hereby incorporated by reference.
1. Field of the Invention
This invention relates to thin film transistor array substrates of the type used in liquid crystal displays. More particularly, this invention relates to a thin film transistor array substrate, and to its manufacturing method, that is fabricated using a reduced number of masks.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance using an electric field to produce an image. To this end, an LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal cells.
The liquid crystal display panel includes a thin film transistor array substrate and an opposed color filter array substrate. Spacers between two substrates main a constant cell gap, which is filled by a liquid crystal.
The thin film transistor array substrate has gate lines and data lines, thin film transistor switching devices at intersections of the gate lines and the data lines, pixel electrodes in liquid crystal cells defined by the crossing gate and data lines, with the pixel electrodes being connected to the thin film transistors, and alignment films. The gate lines and the data lines receive signals from driving circuits via pad portions. The thin film transistors apply pixel voltages on the data lines to the pixel electrodes in response to scanning signals applied to the gate lines.
The color filter array substrate consists of color filters for the liquid crystal cells, a black matrix that divides the color filters, a common electrode for applying a reference voltage to the liquid crystal cells, and an alignment film.
The liquid crystal display panel is made by preparing the thin film array substrate and the color filter array substrate individually, joining them, injecting a liquid crystal between those substrates, and then sealing the liquid crystal in place.
Since fabricating a thin film transistor array substrate requires multiple masking processes, manufacturing a thin film transistor array substrate is a major factor in the costs of a liquid crystal display panel. To reduce costs, significant effort has gone into reducing the required number of masking processes. This is because each mask process includes many sub-processes, such as deposition, cleaning, photolithography, etching, photoresist stripping and inspection. While the standard thin film transistor array substrate manufacturing process used five masks, a newer four-mask process has been developed.
FIG. 1 is a plan view illustrating a thin film transistor array substrate made by the four-mask process, and FIG. 2 is a sectional view of the thin film transistor array substrate of FIG. 1 taken along line A-Axe2x80x2. The thin film transistor array substrate includes crossing gate lines 2 and data lines 4 on a lower substrate 42. A gate insulating film 44 separates the gate and data lines 2 and 4. A thin film transistor 6 is provided at each intersection, and pixel electrodes 18 are provided in liquid crystal cells defined by the gate and data lines 2 and 4. The thin film transistor array substrate includes storage capacitors 20 formed by overlaps of pixel electrodes 18 and gate lines 2. Additionally, gate pad portions 26 connect to the gate lines 2, and data pad portions 34 connects to the data lines 4.
Each thin film transistor 6 includes a gate electrode 8 that is connected to a gate line 2, a source electrode 10 that is connected to a data line 4, a drain electrode 12 that is connected to a pixel electrode 18, and an active layer 14 that overlap the gate electrode 8 and that defines a channel between the source electrode 10 and the drain electrode 12. The thin film transistor 6 allows a pixel voltage signal applied to the data line 4 to be applied to the pixel electrode and sustained on a storage capacitor in response to a gate signal applied to the gate line 2. The active layer 14 also overlaps the data pad 36, the storage electrode 22, and the data line 4. On the active layer 14 is an ohmic contact layer 48 for making an ohmic contact.
As shown in FIG. 1 and FIG. 2, the pixel electrode 18 is connected, via a first contact hole 16 through a protective film 50, to the drain electrode 12. The pixel electrode 18 is used for producing a potential difference with respect to a common electrode on the upper substrate (not shown) when charged with a pixel voltage. This potential difference rotates the liquid crystal between the thin film transistor array substrate and the upper substrate owing to dielectric anisotropy. Thus, the pixel voltage controls the amount of light emitted by the upper substrate from a light source input through the pixel electrode 18.
The storage capacitor 20 includes part of a xe2x80x9cpre-stagexe2x80x9d gate line 2. The storage capacitor 20 also includes a storage electrode 22 that overlaps the gate line 2, an interposed gate insulating film 44, an interposed active layer 14, and an interposed ohmic contact layer 48. A pixel electrode 22 on the protective film 50 contacts the storage electrode 22 through a second contact hole 24. The storage capacitor 20 maintains the pixel voltage on the pixel electrode 18 until the next pixel voltage is applied.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 includes a gate pad 28, which extends from the gate line 2, and a gate pad protection electrode 32 that is connected, via a third contact hole 30 through the gate insulating film 44 and through the protective film 50, to the gate pad 28.
The data line 4 is connected, via the data pad portion 34, to a data driver (not shown). The data pad portion 34 includes a data pad 36 that extends from the data line 4, and a data pad protection electrode 40 that is connected, via a fourth contact hole 38 through the protective film 50, to the data pad 36.
Hereinafter, a method of fabricating the thin film transistor substrate of FIG. 1 and FIG. 2 will be described with reference to FIG. 3A to FIG. 3D. Referring to FIG. 3A, gate patterns are provided on the lower substrate 42. To do so, a gate metal layer is formed on the upper substrate 42 by deposition, possibly sputtering. Then, the gate metal layer is patterned by photolithography and etching using a first mask process to form the gate line 2, the gate electrode 8, and the gate pad 28. The gate metal layer can be a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo), or aluminum.
Referring to FIG. 3B, the gate insulating film 44, the active layer 14, the ohmic contact layer 48, and source/drain patterns are sequentially formed on the structure shown in FIG. 3A. To do so, the gate insulating film 44, an undoped amorphous silicon layer, an n+ amorphous silicon layer, and source/drain metal layer are sequentially provided by deposition, beneficially plasma enhanced chemical vapor deposition (PECVD) or sputtering. Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at the channel region of the thin film transistor is used as a second mask. This allows the photo-resist pattern at channel regions to have a lower height than the remainder of the photoresist. Subsequently, the source/drain metal layer is patterned using a wet etching process to provide source/drain patterns that include the data line 4, the source electrode 10, the drain electrode 12 (which at this time is integral with the source electrode 10), and the storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned using a dry etching process and using the same photo-resist pattern to provide the ohmic contact layer 48 and the active layer 14. The photo-resist pattern with the relatively low height is removed from the channel portion by an ashing process. Thereafter, the source/drain pattern and the ohmic contact layer 48 at the channel portion are etched by a wet etching process. Thus, part of the active layer 14 is exposed, thus disconnecting the source electrode 10 from the drain electrode 12 (until a conductive channel is formed). Then, the remaining photo-resist pattern is removed by a stripping process. The gate insulating film 14 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is molybdenum (Mo), titanium (Ti), tantalum (Ta), or a molybdenum alloy.
Referring to FIG. 3C, the protective film 50 having the first through the fourth contact holes 16, 24, 30 and 38 are formed on the structure shown in FIG. 3B. The protective film 50 is provided by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film 50 is then patterned by photolithography using a third mask and an etch process to define the first to the fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed through the protective film 50 to expose a portion of the drain electrode 12. The second contact hole 24 is formed through the protective film 50 and to expose a portion the storage electrode 22. The third contact hole 30 is formed through the protective film 50 and through the gate insulating film 44 to expose a portion of the gate pad 28. The fourth contact hole 38 is formed through the protective film 50 to expose a portion of the data pad 36. The protective film 50 is made from an inorganic material that is identical to the gate insulating film 44, or from an organic material having a small dielectric constant, such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring now to FIG. 3D, transparent electrode patterns are then provided on the protective film 50. To do so, a transparent electrode material is deposited on the structure shown in FIG. 3C using a deposition technique such as sputtering. Then, the transparent electrode material is patterned by photolithography using a fourth mask and an etching process to provide the transparent electrode patterns. That pattern includes the pixel electrode 18, the gate pad protection electrode 32, and the data pad protection electrode 40. The pixel electrode 18 is electrically connected via the first contact hole 16 to the drain electrode 12, and to the storage electrode 22 via the second contact hole 24. Additionally, the pixel electrode 18 overlaps part of the pre-stage gate line 2. The gate pad protection electrode 32 is electrically connected via the third contact hole 30 to the gate pad 28. The data pad protection electrode 40 is electrically connected via the fourth contact hole 38 to the data pad 36. The transparent electrode material is comprised of indium-tin-oxide (ITO), tin-oxide (TO), or of indium-zinc-oxide (IZO).
As described above, the conventional four-round mask process thin film transistor substrate is simpler than the prior five-round mask process. Hence manufacturing costs are reduced. However, the four-round mask process might not be optimal. Therefore, a novel thin film transistor array substrate, and a novel manufacturing method thereof, that have even simpler manufacturing processes would be beneficial.
Accordingly, it is an object of the present invention to provide a thin film transistor array substrate, and a manufacturing method thereof, using a three-round mask process.
To achieve these and other objects of the present invention, a thin film transistor array substrate according to one aspect of the present invention includes crossing gate and data lines having a gate insulating pattern therebetween; pixel electrode formed at cell areas defined by the crossing gate and data lines; and thin film transistors. Each thin film transistor includes a gate electrode that is connected to a gate line, a source electrode that is connected to a data line, a drain electrode that is connected a pixel electrode, and a semiconductor pattern for providing a channel between the source electrode and the drain electrode. Additionally, a gate pad portion that includes a lower gate pad and an upper gate pad connect to the gate line, and a data pad portion that includes a lower data pad and an upper data pad connect to the data line. The gate patterns, including the gate line, the gate electrode, the lower gate pad, and the lower data pad, are comprised of a transparent electrode pattern and of a gate metal pattern. Each of the source/drain patterns, including the data line, the source electrode, the drain electrode, the upper gate pad, and the upper data pad are comprised of a source/drain metal. The semiconductor pattern extends along the data line and along the gate line (together with the gate insulating pattern). However, the semiconductor pattern is opened between liquid crystal cells.
The thin film transistor array substrate further includes storage capacitors, each of which is comprised of part of a gate line, a storage electrode that overlaps the gate line, part of the gate insulating pattern, and part of the semiconductor pattern. The storage capacitor is electrically connected to the pixel electrode.
Alternatively, the thin film transistor array substrate has a storage capacitor comprised of part of the gate line, a storage electrode that overlaps the gate line, and part of the gate insulating pattern. Again, the storage capacitor is electrically connected to the pixel electrode.
In the thin film transistor array substrate, the semiconductor pattern on the gate insulating pattern is removed such that the gate insulating pattern is exposed.
The gate pad portions are formed such that a transparent electrode pattern is exposed through a first hole that passes through the gate metal pattern in the upper gate pad and in the lower gate pad. The data pad portion is formed such that the transparent electrode pattern is exposed through a second hole that passes through the gate metal pattern in the upper data pad and in the lower data pad.
The thin film transistor array substrate is protected by an alignment film that is provides for a liquid crystal alignment.
A method of manufacturing a thin film transistor array substrate according to another aspect of the present invention includes forming gate patterns on a substrate using a first mask process. The gate patterns include a gate line comprised of a transparent metal pattern and of a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode. Then, a second mask process that forms a gate insulating pattern and a semiconductor pattern is used. Then, a third mask that forms source/drain patterns is used. The source/drain patterns include data lines, source electrodes, drain electrodes, upper gate pads, and upper data pads. Also, in the second mask process the gate metal patterns on the upper portions of the pixel electrodes are removed.
The third mask process includes forming storage electrodes over the gate insulating film and over the semiconductor patterns. Each storage electrode overlaps part of the gate line. Additionally, each storage electrode electrically connects to a pixel electrode.
The second mask process includes disposing a gate insulating layer and a semiconductor layer on the substrate; forming a photo-resist pattern that includes a first area and a second area having a lower height than the first area. A diffractive exposure mask or a semi-transmitting mask can be used. Then, the photo-resist pattern is used to etch the gate insulating layer. Also, thin film transistor areas comprised of gate electrodes, source electrodes, drain electrodes, the gate insulating pattern, and the semiconductor patterns that overlap the gate line and the data line are formed by etching. Then, the second area of the photo-resist pattern is removed by an ashing process. Thereafter, etching is performed on the newly exposed portion of the semiconductor pattern to expose the gate insulating pattern. Then, the remaining photo-resist pattern is removed.
The area from which the semiconductor pattern is removed to expose the gate insulating pattern includes the remaining area excluding an area overlapping the source electrode, the drain electrode and the channel portion between the source electrode and the drain electrode; and a partial area between the cells in the gate line.
When the semiconductor pattern is removed, the semiconductor pattern overlapped by the storage electrode can also be removed.